发明名称 Apparatus and method to accelerate the testing of a memory array by applying a selective inhibition of address input lines.
摘要 The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines (addr_in_0, addr_in_1, ...) for selecting a row according to a particular address given on the address input lines. Additional address mask input lines (addr_msk_0, addr_msk_1, ...) are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line (addr_in_0, addr_in_1, ...). The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.
申请公布号 EP3021326(A1) 申请公布日期 2016.05.18
申请号 EP20140193480 申请日期 2014.11.17
申请人 EM MICROELECTRONIC-MARIN SA 发明人 PLAVEC, LUBOMIR;MARINELLI, FILIPPO;KUBAR, MILOSLAV
分类号 G11C29/18;G11C29/34 主分类号 G11C29/18
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