发明名称 LINK LAYER SIGNAL SYNCHRONIZATION
摘要 A clock synchronization logic to compare a core clock of the apparatus having a core clock frequency against a transmission clock of the apparatus having a first frequency or a reception clock of the apparatus having a second frequency, and, based on results of the comparison, generate a synchronized link transfer transmission clock or a synchronized link transfer reception clock respectively. Other embodiments may be described and/or claimed.
申请公布号 KR20160055685(A) 申请公布日期 2016.05.18
申请号 KR20150141433 申请日期 2015.10.08
申请人 INTEL CORPORATION 发明人 BIRRITTELLA MARK S.
分类号 G06F1/12;G06F13/14 主分类号 G06F1/12
代理机构 代理人
主权项
地址