| 发明名称 | Method for fabricating enhancement mode transistor | ||
| 摘要 | A method for making an enhancement-mode transistor is described. The method includes forming a first III-V compound layer on a substrate and forming a second III-V compound layer on the first III-V compound layer. The second III-V compound layer is different from the first III-V compound layer. A gate stack is formed thereon. The forming of the gate stack further includes forming a diode having a pair of a n-type doped III-V compound layer and a p-type doped III-V compound layer. Source and drain features are formed on the second III-V compound layer and interposed by the gate stack. | ||
| 申请公布号 | US9343542(B2) | 申请公布日期 | 2016.05.17 |
| 申请号 | US201414550521 | 申请日期 | 2014.11.21 |
| 申请人 | Taiwan Semiconductor Manufacturing Company, Ltd. | 发明人 | Kalnitsky Alexander;Hsiung Chih-Wen;Tsai Chun Lin |
| 分类号 | H01L21/338;H01L21/322;H01L29/66;H01L29/205;H01L29/207;H01L21/02;H01L29/10;H01L29/20;H01L29/423;H01L29/778 | 主分类号 | H01L21/338 |
| 代理机构 | Haynes and Boone, LLP | 代理人 | Haynes and Boone, LLP |
| 主权项 | 1. A method, comprising: forming a first Group III-V compound layer on a substrate; forming a second Group III-V compound layer on the first Group III-V compound layer, wherein the second Group III-V compound layer is different from the first Group III-V compound layer; forming a gate stack on the second Group III-V compound layer, wherein the gate stack includes: forming a diode having a pair of a n-type doped Group III-V compound layer and a p-type doped Group III-V compound layer;forming a dielectric layer over the diode; andforming a metal layer on the diode and the dielectric layer; and forming source and drain feature on the second Group III-V compound layer and interposed by the gate stack. | ||
| 地址 | Hsin-Chu TW | ||