发明名称 Discrete time compensation mechanisms
摘要 Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous data from which the time slots are sampled from and for processing the sampled data through the plurality of channels faster than the continuous data is being received. Compensations for one or more gaps are generated based on a set of predetermined criteria and a corrected time stamp is applied to the sampled data for processing among different processing channels.
申请公布号 US9344209(B2) 申请公布日期 2016.05.17
申请号 US201314016534 申请日期 2013.09.03
申请人 APPLIED MICRO CIRCUITS CORPORATION 发明人 Nichols Stacy;Gandhi Sameer;Christian Burt
分类号 H04J3/06 主分类号 H04J3/06
代理机构 Amin, Turocy & Watson LLP 代理人 Amin, Turocy & Watson LLP ;Turocy Gregory
主权项 1. A data processing system comprising: one or more data stores (memory component), wherein at least one data store is configured to receive and store data obtained from a continuous data stream; at least one processor communicatively coupled to at least one of the one or more data stores; at least one channel component communicatively coupled to the one or more data stores and the at least one processor, the at least one channel component being configured for determining which channel of a plurality of channels to process time slots of sampled data from the continuous data stream stored in the one or more data stores, wherein the sampled data is time stamped in a discrete time domain; a common channel clock component and a real time clock, each communicatively coupled to the at least one of the plurality of channels, the common channel clock configured for time stamping time slots of the sampled data faster in the discrete time domain than the real time clock, and for processing the sampled data faster than the data is being received; and at least one compensation component communicatively coupled to the at least one channel of the plurality of channels, the at least one compensation component configured for compensating for gaps in the sampled data and after compensating, applying a corrected time stamp to the sampled data, wherein the compensation component comprises: a plurality of per channel time of day counter components that correspond to a plurality of channels, and configured for incrementing based on an increment value that is independent per channel among the plurality of channels respectively;a reference clock component that is configured for time stamping data being received in a non-discrete time domain; anda master time of day counter component configured for synchronizing the plurality of per channel time of data counter components, and is synchronized to the reference clock component.
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