Stress mitigation structure for wafer warpage reduction

摘要

An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation.

主权项

1. An integrated device comprising:
a substrate supporting a first interlayer dielectric; a first conductive stack comprising a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate, wherein the first conductive stack comprises a first conductive layer directly on a surface of the substrate, the first interlayer dielectric directly on surfaces of the first conductive layer, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and a third conductive layer directly on the first interlayer dielectric and coupled to the first conductive layer through a first via as the BEOL conductive layer at the first elevation; and a second conductive stack comprising the BEOL conductive layer at a second elevation relative to the substrate that differs from the first elevation, wherein the second conductive stack comprises the third conductive layer directly on the surface of the substrate as the BEOL conductive layer at the second elevation.