Electronic device and data control method

摘要

The disclosure provides an electronic device including a coupler, a transceiver, and a control circuit. The coupler generates a coupled downlink signal according to a downlink signal from a head-end unit. The transceiver switches between the transmission of a downlink signal and the reception of an uplink signal according to a control signal. The control circuit receives the coupled downlink signal, generates a status counting signal according to the power status of the coupled downlink signal, and generates the control signal according to the status counting signal. Only when the level of the coupled downlink signal is lower than an amplitude threshold level with a duration longer than a status counting time, the control circuit converts the status counting signal from a first logic level to a second logic level opposite to the first logic level. Otherwise, the control circuit maintains the status counting signal on the first logic level.

主权项

1. An electronic device, arranged to receive at least one downlink signal and transmit at least one uplink signal, the electronic device comprising:
a coupler, arranged on a downlink path, and arranged to generate a coupled downlink signal according to the downlink signal from a head-end unit (HEU); a transceiver, arranged to switch between the transmission of the downlink signal and the reception of the uplink signal according to a control signal; and a control circuit, arranged to:
receive the coupled downlink signal,generate a status counting signal according to a power of the coupled downlink signal, andgenerate the control signal according to the status counting signal and transmit the control signal to the transceiver, wherein only when a level of the coupled downlink signal is lower than an amplitude threshold value and longer than a status counting time, the control circuit advances the time of switching the status control signal from a first logic level to a second logic level opposite to the first logic level by a time sequence adjusting time, otherwise the control circuit maintains the status control signal on the first logic level, and postponing the time sequence adjusting time by a delay time.