Stacked wafer-level package device

摘要

Wafer-level package devices are described that include multiple die packaged into a single wafer-level package device. In an implementation, a wafer-level package device includes a semiconductor device having at least one electrical interconnection formed therein. At least one semiconductor package device is positioned over the first surface of the semiconductor device. The semiconductor package device includes one or more micro-solder bumps. The wafer-level package device further includes an encapsulation structure disposed over and supported by the semiconductor device for encapsulating the semiconductor package device(s). When the semiconductor package device is positioned over the semiconductor device, each micro-solder bump is connected to a respective electrical interconnection that is formed in the semiconductor device.

主权项

1. A wafer-level package device comprising:
a semiconductor device having at least one electrical interconnection and at least one integrated circuit formed therein, the semiconductor device including a first surface and a second surface, where the at least one electrical interconnection includes at least one micro-through-silicon-via, where the at least one micro-through-silicon via has a size from ten (10) micrometers to fifty (50) micrometers and a depth from fifty (50) micrometers to one hundred and fifty (150) micrometers; a semiconductor package device positioned over the first surface of the semiconductor device; at least one micro-solder bump coupled to the semiconductor package device and coupled to the micro-through-silicon via; and a single encapsulation structure supported by the semiconductor device that encapsulates all sides of the semiconductor package device including a side of the semiconductor package device that is distal from the semiconductor device, where the encapsulation structure includes a polymer, and where the encapsulation structure abuts the semiconductor device including at least one integrated circuit, wherein the at least one micro-solder bump is in contact with the at least one electrical interconnection when the semiconductor package device is positioned over the first surface of the semiconductor device and the at least one electrical interconnection is configured to provide electrical connectivity to the semiconductor package device.