Package substrates, semiconductor packages including the same, electronic systems including the same, and memory cards including the same

摘要

A package substrate includes a core layer, first external interconnection lines on a top surface of the core layer, and internal interconnection lines. The first external interconnection lines include a first outermost external interconnection line on an edge of the core layer, and the internal interconnection lines include an outermost internal interconnection line in the edge of the core layer. A first bonding pad is disposed on the first outermost external interconnection line and exposed in a first bonding region of the core layer. A second bonding pad is disposed on the outermost internal interconnection line and exposed in a second bonding region of the core layer. The first bonding region is spaced apart from a chip attachment region by a first distance, and the second bonding region is spaced apart from the chip attachment region by a second distance greater than the first distance.

主权项

1. A package substrate comprising:
a substrate core layer; a plurality of first external circuit interconnection lines disposed on a top surface of the substrate core layer, the plurality of first external circuit interconnection lines including a first outermost external circuit interconnection line located on the substrate core layer and adjacent to an edge of the substrate core layer; a plurality of internal circuit interconnection lines disposed in the substrate core layer, the plurality of internal circuit interconnection lines including an outermost internal circuit interconnection line located in the substrate core layer and adjacent to the edge of the substrate core layer; a first bonding pad disposed on the first outermost external circuit interconnection line and exposed in a first bonding region of the substrate core layer; and a second bonding pad disposed on the outermost internal circuit interconnection line and exposed in a second bonding region of the substrate core layer, wherein the first bonding region is spaced apart from a chip attachment region by a first distance, and the second bonding region is spaced apart from the chip attachment region by a second distance, the second distance being greater than the first distance.