发明名称 |
Acquisition device with multistage digital equalization |
摘要 |
An acquisition device includes an analog to digital converter (ADC) composed of multiple interleaved ADCs (sub-ADCs), which receives an analog signal which is converted to digital form. The digitized signal is processed seriatim by a pre-(or trigger-) equalizer, an acquisition memory and a post-(or memory) equalizer. In a calibration mode, frequency responses of the respective sub-ADCs are determined and trigger coefficients are determined for application to the trigger equalizer to effect a preliminary equalization of the digitized signal sufficient to permit operation of the trigger processor in an acquisition mode. Memory coefficients are determined based on residual frequency responses of the sub-ADCs, for application to the memory equalizer. A trigger processor is responsive to the trigger equalizer to select a subset of samples of the digitized signal for loading to the acquisition memory. The trigger equalizer and a memory equalizer are configured for consecutive operation so that, in an acquisition mode, the memory equalizer receives as its input, a digitized signal from the ADC that has been pre-processed in the trigger equalizer, and the memory equalizer corrects only the residue of misalignments and frequency distortions that remain after the trigger equalizer operation. |
申请公布号 |
US9344301(B2) |
申请公布日期 |
2016.05.17 |
申请号 |
US201514725535 |
申请日期 |
2015.05.29 |
申请人 |
Guzik Technical Enterprises |
发明人 |
Guzik Nahum;Stein Anatoli B.;Volfbeyn Semen P.;Tarnikov Igor |
分类号 |
H04L25/03;H04L25/06;H04B1/10 |
主分类号 |
H04L25/03 |
代理机构 |
Burns & Levinson LLP |
代理人 |
Burns & Levinson LLP ;Maraia Joseph M. |
主权项 |
1. An acquisition device for multistage digital equalization comprising;
A. a composite analog to digital converter (ADC) including a plurality of interleaved sub-ADCs, the ADC having an analog input common to the sub-ADCs, wherein each sub-ADC has an associated sub-ADC output, and wherein each sub-ADC is characterized by an associated frequency response, each sub-ADC being responsive to an analog signal at the analog input, to generate at its associated sub-ADC output, a sequence of digital samples weighted by the associated frequency response of the sub-ADC and otherwise corresponding to instantaneous values of the analog signal at the analog input at a system sampling rate;
wherein the frequency responses of the respective sub-ADCs are characterized by mutual misalignments from sub-ADC to sub-ADC, and a composite frequency response of the composite analog to digital converter as a whole is characterized by frequency response distortion; B. a frequency responses measurer having measurer inputs connected to the respective sub-ADC outputs, and measurements outputs, the measurer being responsive to the respective sub-ADC outputs to measure the frequency responses of the respective sub-ADCs and to generate at the respective measurements outputs, measurement signals representative of the frequency responses of the respective sub-ADCs; C. a pre-equalizer coefficients calculator having pre-equalizer coefficients inputs connected to the respective measurer outputs, and pre-equalizer coefficients outputs wherein the pre-equalizer coefficients calculator is responsive to the measurer outputs to generate pre-equalizer coefficients at the pre-equalizer coefficients outputs;
wherein the pro-equalizer coefficients are determined for effecting partial reduction of misalignments of the respective sub-ADC outputs and partial reduction of frequency response distortion associated with the composite analog to digital converter as a whole; and D. a pre-equalizer having pre-equalizer inputs connected to the respective sub-ADC outputs of the composite analog to digital converter, pre-equalizer coefficients inputs for receiving the pre-equalizer coefficients from the pro-equalizer coefficient outputs of the pre-equalizer coefficients calculator, and pre-equalizer outputs, wherein the pre-equalizer is responsive to the respective sub-ADC outputs and the pre-equalizer coefficients, to generate at the pre-equalizer outputs, pre-equalized signals including components corresponding to the respective sub-ADC outputs wherein the components are characterized by the partial reduced misalignments with respect to the respective sub-ADC outputs, and the partial reduced frequency response distortion relative the frequency response distortion associated with the composite analog to digital converter as a whole. |
地址 |
Mountain View CA US |