Dual-gate transistor control based on calibration circuitry

摘要

Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.

主权项

1. A method of controlling dual-gate transistors, the method comprising:
a) activating a calibration sequence having first and second phases in response to a calibration command signal; b) during the first phase, increasing a first data input at a signal gate of a first dual-gate transistor by an adjustment voltage, and storing a first result; c) during the second phase, decreasing the first data input, and storing a second result; and d) using the first and second results to set first and second control signals, wherein the first control signal is coupled to a control gate of the first dual-gate transistor, and the second control signal is coupled to a control gate of a second dual-gate transistor.