Successive approximation analog-to-digital converter and conversion method thereof

摘要

A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.

主权项

1. A successive approximation analog-to-digital converter comprising a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit, wherein:
said segmented-multiple-stage capacitor array with redundancy bits is used for sampling input voltage and generating output voltage Vout+ and Vout− under the control of said control logic circuit; the segmented-multiple-stage capacitor array with redundancy bits comprises the first stage capacitor array, the second stage capacitor array, . . . , the m stage capacitor array, the first-segment capacitor C1, the second-segment capacitor C2, . . . , the m-1 segment capacitor C(m-1); each of the previous m-1 stages of capacitor arrays comprises no less than 1 redundancy bit; the minimum number of redundancy bit required by the m stage capacitor array depends on the maximum of capacitor mismatch caused by process capability, wherein m is a positive integer no less than 2; said comparator is employed to compare output voltages Vout+ and Vout− and generate a result; said weight-storage circuit is employed to store the weight of each capacitor unit of segmented-multiple-stage capacitor array with redundancy bits; said code reconstruction circuit is employed for successive approximation analog-to-digital converter to calculate an output code according to the output from the comparator and the capacitor's weight from weight-storage circuit; and said control logic circuit is employed to control the foregoing segmented-multiple-stage capacitor array with redundancy bits, comparator, weight-storage circuit and code reconstruction circuit.