Method for manufacturing thin film transistor array substrate

摘要

A method for manufacturing a thin film transistor (TFT) array substrate having enhanced reliability is disclosed. The method includes forming a multilayer structure including at least one first metal layer and a second metal layer made of copper, forming a first mask layer including a first mask area corresponding to a data line and a second mask area corresponding to an electrode pattern to overlap with an active layer, patterning the multilayer structure, thereby forming the data line constituted by the multilayer structure, patterning the second metal layer, thereby forming the electrode pattern constituted by the at least one first metal layer, forming a second mask layer to expose a portion of the electrode pattern corresponding to a channel area of the active layer, patterning the at least one first metal layer, thereby forming source and drain.

主权项

1. A method for manufacturing a thin film transistor array substrate including gate and data lines intersecting with each other to define a plurality of pixel areas, comprising:
forming, on the substrate, the gate lines and gate electrodes respectively branched from corresponding ones of the gate lines to the pixel areas; forming, over the substrate, a gate insulating film to cover the gate lines and the gate electrodes; forming, on the gate insulating film, active layers to overlap with the gate electrodes, respectively; forming, over the gate insulating film, a multilayer structure including at least one first metal layer and a second metal layer made of copper (Cu); forming, on the multilayer structure, a first mask layer including first mask areas having a first height and second mask areas having a second height which is lower than the first height, the first mask areas respectively corresponding to the data lines, the second mask areas respectively corresponding to electrode patterns, each electrode pattern corresponding to a source electrode, a drain electrode, and a channel area of the active layer, and the channel area of the active layer corresponding to a space between the source electrode and the drain electrode; patterning the multilayer structure under condition that the first mask layer has been formed, thereby forming the data lines constituted by the multilayer structure; ashing the first mask layer such that the first mask areas have a third height lower than the first height and the second mask areas are removed; patterning the second metal layer under condition that the first mask areas having the third height have been formed, thereby forming the electrode patterns constituted by the at least one first metal layer but not by the second metal layer made of copper; removing the first mask areas having the third height; forming, on the gate insulating film, a second mask layer to expose portions of the electrode patterns respectively corresponding to the channel areas of the active layers; and patterning the electrode patterns constituted by the at least one first metal layer under condition that the second mask layer has been formed, thereby forming the source and drain electrodes spaced from each other at opposite sides of each channel area of corresponding ones of the active layers.