发明名称 Three-dimensional devices having reduced contact length
摘要 Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed starting adjacent to a surface of a substrate. Peripheral circuitry is formed on an elevated portion that is adjacent to the memory array and has an uppermost portion substantially coplanar with an uppermost surface of the memory array. Additional apparatuses and methods are described.
申请公布号 US9343479(B2) 申请公布日期 2016.05.17
申请号 US201514615830 申请日期 2015.02.06
申请人 Micron Technology, Inc. 发明人 Tanzawa Toru
分类号 H01L27/115 主分类号 H01L27/115
代理机构 Schwegman Lundberg & Woessner, P.A. 代理人 Schwegman Lundberg & Woessner, P.A.
主权项 1. A method of forming a memory apparatus, the method comprising: forming a memory array having a first surface proximate to a surface of a substrate and a second surface distal to the surface of the substrate, the memory array including: forming a number of levels of semiconductor material and a number of levels of dielectric material, each of the levels of semiconductor material being separated from a respective adjacent one of the levels of semiconductor material by at least a respective one of the levels of dielectric material; forming peripheral circuitry for the memory array, including: forming an elevated portion adjacent to a peripheral edge of the substrate and adjacent to the memory array;forming devices for interfacing with the memory array adjacent to a surface of the elevated portion that is more distal to the surface of the substrate than the first surface of the memory array; andforming an upper surface of the peripheral circuitry to be substantially coplanar with an upper surface of the memory array to reduce an overall height of peripheral circuitry contacts to couple the peripheral circuitry contacts from the peripheral circuitry to respective ones of a plurality of interconnects; and forming the plurality of interconnects between the memory array and the peripheral circuitry.
地址 Boise ID US