发明名称 |
Receiving circuit |
摘要 |
A receiving circuit includes circuits arranged in parallel, each circuits including a voltage-controlled-oscillator (VCO) configured to generate a clock having an oscillation frequency according to an inductor and a capacitor, and a gain circuit. Each circuit is configured to sample a piece of input data with an output clock of the VCO and adjust the oscillation frequency of the VCO based on a phase difference and a frequency difference between the piece of input data and the output clock, thereby recovering data and a clock based on the piece of input data. The gain circuit is configured to adjust ratios of gains of up and down of the oscillation frequency of the VCO in a loop in each circuit arranged adjacent to each other, based on a phase difference between the pieces of input data and a phase difference between the output clocks of the respective circuits. |
申请公布号 |
US9344269(B2) |
申请公布日期 |
2016.05.17 |
申请号 |
US201514681794 |
申请日期 |
2015.04.08 |
申请人 |
Fujitsu Limited |
发明人 |
Shibasaki Takayuki |
分类号 |
H04L7/033;H03L7/089;H03B5/12;H03L7/07;H03L7/093 |
主分类号 |
H04L7/033 |
代理机构 |
Arent Fox LLP |
代理人 |
Arent Fox LLP |
主权项 |
1. A receiving circuit comprising:
a plurality of clock-and-data recovery circuits arranged in parallel, each clock-and-data recovery circuit including an LC voltage controlled oscillator configured to generate a clock having an oscillation frequency according to an inductor and a capacitor, and each clock-and-data recovery circuit being configured to sample a piece of input data with an output clock of the LC voltage controlled oscillator and adjust the oscillation frequency of the LC voltage controlled oscillator in accordance with a phase difference and a frequency difference between the piece of input data and the output clock of the LC voltage controlled oscillator, thereby recovering data and a clock based on the piece of input data; and a gain adjustment circuit configured to adjust ratios of gains of up and down of the oscillation frequency of the LC voltage controlled oscillator in a loop in each of the clock-and-data recovery circuits arranged adjacent to each other, in accordance with a phase difference between the pieces of input data and a phase difference between the output clocks of the respective clock-and-data recovery circuits. |
地址 |
Kawasaki JP |