Clock signal distribution power efficiency improvement

摘要

A circuit may include a pulse generation circuit configured to receive a first clock signal with a first-clock rate and a first-clock duty cycle. The pulse generation circuit may be configured to generate, based on the first clock signal, a pulse signal with a pulse frequency and with a pulse duty cycle that is smaller than the first-clock duty cycle. The circuit may also include a sub-harmonic injection locking oscillator configured to receive the pulse signal. The sub-harmonic injection locking oscillator may be configured to output, based on the pulse signal, a second clock signal with a second-clock rate that is greater than the first-clock rate and greater than the pulse frequency.

主权项

1. A circuit comprising:
a clock generator configured to generate a first clock signal with a first-clock rate and a first-clock duty cycle; a clock distributor electrically coupled to the clock generator and including one or more buffers configured to receive the first clock signal generated by the clock generator and to distribute the first clock signal at the first-clock rate and the first-clock duty cycle; a pulse generation circuit electrically coupled to the clock distributor and configured to receive the first clock signal distributed by the clock distributor and configured to generate, based on the first clock signal, a pulse signal with a pulse frequency and with a pulse duty cycle that is smaller than the first-clock duty cycle; and a sub-harmonic injection locking oscillator electrically coupled to the pulse generation circuit and configured to receive the pulse signal and to output, based on the pulse signal, a second clock signal with a second-clock rate that is greater than the first-clock rate and greater than the pulse frequency, wherein the pulse generation circuit and the sub-harmonic injection locking oscillator are included on a same encapsulated silicon die.