Integrated circuit comprising frequency change detection circuitry

摘要

Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

主权项

1. An integrated circuit (IC), comprising:
a multiplying injection-locked oscillator (MILO), wherein the MILO generates a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency; a sampler coupled to the MILO, wherein the sampler obtains samples by oversampling the first clock signal using the second clock signal; and a finite state machine (FSM) circuit coupled to the sampler, wherein state transitions in the FSM are triggered based on the samples, and wherein a change in the first clock frequency is detected when a corresponding state transition is triggered in the FSM circuit.