发明名称 Dual channel vertical field effect transistor including an embedded electrode
摘要 A device is disclosed including one or more field effect transistors, each field effect transistor including: an elongated drain contact line including an electrically conductive material extending along a first horizontal direction; a drain including a first conductivity type semiconductor region overlaying the drain contact line; a source including a the first conductivity type semiconductor region located above the drain; and a gate extending vertically between the drain and the source. Each field effect transistor may include a first channel and a second channel, each including a second conductivity type
申请公布号 US9343507(B2) 申请公布日期 2016.05.17
申请号 US201414206196 申请日期 2014.03.12
申请人 SANDISK 3D LLC 发明人 Takaki Seje
分类号 H01L29/76;H01L27/24;H01L29/78;H01L29/66;H01L27/115;H01L29/788;H01L27/112;H01L29/792;H01L29/423;H01L29/10;H01L45/00;H01L29/49 主分类号 H01L29/76
代理机构 The Marbury Law Group PLLC 代理人 The Marbury Law Group PLLC
主权项 1. A device comprising one or more field effect transistors, each field effect transistor comprising: an elongated drain contact line comprising an electrically conductive material extending along a first horizontal direction; a drain comprising a first conductivity type semiconductor region overlaying the drain contact line; a source comprising a first conductivity type semiconductor region located above the drain; a gate extending vertically between the drain and the source, wherein: the gate is elongated along a second horizontal direction transverse to the first horizontal direction;the gate comprises a first vertical side and an opposing second vertical side, each vertical side contacting a gate insulating material;the gate comprises a top portion adjacent to the source and electrically insulated from the source by a gate top isolation layer of insulating material; andthe gate comprises a bottom portion adjacent to the drain and electrically insulated from the drain by a gate bottom isolation layer of insulating material; and a first channel and a second channel, each comprising a second conductivity type semiconductor region different from the first conductivity type, wherein: the first channel extends vertically from the drain to the source and is located on the first vertical side of the gate and is electrically insulated from the gate by the gate insulating material contacting the first vertical side of the gate; the second channel extends vertically from the drain to the source and is located on the second vertical side of the gate and is electrically insulated from the gate by the gate insulating material contacting the second vertical side of the gate; and the source, the first channel and the second channel collectively constitute a pillar having a single continuous top surface such that a first sidewall surface of the pillar that adjoins a periphery of the top surface of the pillar includes a surface of the first channel and a first surface of the source, and a second sidewall surface of the pillar that adjoins the periphery of the top surface of the pillar includes a surface of the second channel and a second surface of the source.
地址 Milpitas CA US