发明名称 |
Method and structure of monolithically integrated absolute pressure sensor |
摘要 |
An integrated pressure sensing device and method of fabrication thereof are disclosed. The method can include providing a substrate member having a surface region and forming a CMOS IC layer overlying the substrate and forming an oxide layer overlying the CMOS IC layer. A portion of the oxide layer can be removed to form a cavity region. A single crystalline silicon wafer can be bonded overlying the oxide surface region to seal the cavity region. The bonding process can include a fusion bonding or eutectic bonding process. The wafer can be thinned to a desired thickness and portions can be removed and filled with metal materials to form via structures. A pressure sensor device can be formed from the wafer, and can be co-fabricated with another sensor from the wafer. The pressure sensor and the other sensor can share a cavity pressure or have separate cavity pressures. |
申请公布号 |
US9340414(B2) |
申请公布日期 |
2016.05.17 |
申请号 |
US201414311034 |
申请日期 |
2014.06.20 |
申请人 |
mCube Inc. |
发明人 |
Yoneoka Shingo;Flannery, Jr. Anthony F. |
分类号 |
B81C1/00;B81B7/02 |
主分类号 |
B81C1/00 |
代理机构 |
Kilpatrick Townsend & Stockton LLP |
代理人 |
Kilpatrick Townsend & Stockton LLP |
主权项 |
1. A method of fabricating an integrated pressure sensing device, the method comprising:
providing a substrate member having a surface region; forming a CMOS IC layer overlying the surface region, the CMOS IC layer having a CMOS surface region; forming an oxide layer overlying the CMOS surface region, the oxide layer having an oxide surface region; removing at least a portion of the oxide layer to form at least a first cavity region; bonding a single crystalline silicon wafer overlying the oxide surface region to seal the first cavity region; thinning the single crystalline silicon wafer to a desired thickness; removing at least a portion of the single crystalline silicon wafer to form at least one connection path; depositing a metal material within the at least one connection path to form at least one via structure; and removing at least a second portion of the single crystalline silicon wafer to expose a cavity path coupled to the first cavity region, the removed second portion of the single crystalline silicon being outside the sealed first cavity region. |
地址 |
San Jose CA US |