发明名称 System for selecting a task to be executed according to an output from a task control circuit
摘要 The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.
申请公布号 US9342350(B2) 申请公布日期 2016.05.17
申请号 US200612281333 申请日期 2006.08.24
申请人 RENESAS ELECTRONICS CORPORATION 发明人 Maruyama Naotaka
分类号 G06F9/46;G06F9/48;G06F9/52 主分类号 G06F9/46
代理机构 Muncy, Geissler, Olds & Lowe, P.C. 代理人 Muncy, Geissler, Olds & Lowe, P.C.
主权项 1. A task processor comprising: a processor; a plurality of save registers for saving the data in the processor and that are respectively associated with a plurality of tasks and connected to the processor via a plurality of data lines; and a task control circuit that controls switching of tasks and is connected to the processor and the plurality of save registers via signal lines, wherein the processor includes: a processing register that temporarily stores data for execution of a task; andan execution control circuit that loads an instruction and an operand from a memory into the processing register, and to execute the task according to the instruction and operand in the processing register, wherein the execution control circuit includes an instruction decoder that determines whether the instruction to be executed is a predetermined system call instruction or not and transmits a predetermined system call signal to the task control circuit when executing the predetermined system call instruction, the predetermined system call signal not including any information regarding which task to be executed next, and wherein the task control circuit switches between tasks for execution autonomously upon receipt of the system call signal by: causing the data stored in the processing register to be saved in the save register associated with a task being executed,selecting a task to be executed next in accordance with a predetermined rule, by not referring to the system call signal but by referring to context information of each task, andcausing data in the save register associated with the selected task to be loaded into the processing register.
地址 Kawasaki-Shi, Kanagawa JP