发明名称 Switched interface for stacked-die memory architecture with redundancy for substituting defective memory cells
摘要 Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
申请公布号 US9343180(B2) 申请公布日期 2016.05.17
申请号 US201314142565 申请日期 2013.12.27
申请人 Micron Technology, Inc. 发明人 Jeddeloh Joe M.;LaBerge Paul A.
分类号 G11C29/04;G06F13/42;G11C5/02;G11C29/00;G06F13/16 主分类号 G11C29/04
代理机构 Schwegman Lundberg & Woessner, P.A. 代理人 Schwegman Lundberg & Woessner, P.A.
主权项 1. An apparatus, comprising: a plurality of stacked memory dies including a first memory die and a second memory die; a memory vault formed from stacked memory arrays of the plurality of stacked memory dies, the stacked memory arrays including a first memory array in the first memory die and a second memory array in the second memory die, wherein the plurality of stacked memory dies are selected such that addresses associated with contiguous areas of defective memory cells in the first memory die used to form the memory vault do not overlap with addresses associated with another contiguous areas of defective memory cells in the second memory die used to form the memory vault; and a spare memory array included in the memory vault, wherein the memory vault is configured such that at least one first contiguous area of operational memory cells on the spare memory array is located at a starting memory address including at least one of a bank address, a row address, or a column address in common with a second contiguous area of operational memory cells on at least one of the first and second memory dies, wherein the apparatus further comprising a repair decode assessment module to estimate a latency associated with translating a requested memory address to a repair address; and a decision module to cause the requested memory address to be passed to a memory address decoder associated with the memory vault if the latency estimated by the repair decode assessment module is greater than a selected amount.
地址 Boise ID US