MFENCE and LFENCE micro-architectural implementation method and system

摘要

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

主权项

1. A processor comprising:
an instruction prefetch unit to prefetch a cache line of data responsive to a PREFETCH instruction and to store the cache line in a data cache; an instruction fetch unit to fetch a memory load fence (LFENCE) instruction that does not use a mask field thereof, a memory fence (MFENCE) instruction that does not use a mask field thereof, and a cache line flush (CLFLUSH) instruction; a first memory ordering portion of the processor responsive to the LFENCE instruction to prevent newer memory load instructions occurring after the LFENCE instruction in program order from being globally visible before older memory load instructions occurring before the LFENCE instruction in the program order are globally visible without causing the processor to stall dispatch of a newer memory store instruction occurring after the LFENCE instruction in the program order; and a second memory ordering portion of the processor responsive to the MFENCE instruction to prevent a CLFLUSH instruction which follows the MFENCE instruction in program order from being globally visible until a PREFETCH instruction preceding the MFENCE instruction in program order has become globally visible.