Nonvolatile logic array and power domain segmentation in processing device

摘要

A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device.

主权项

1. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:
a plurality of non-volatile logic element arrays; a plurality of volatile storage elements; a processing core; at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements; a first power domain configured to supply power to switched logic elements of the computing device apparatus; wherein a first set of at least one of the plurality of non-volatile logic element arrays is associated with a first function of the computing device apparatus associated with the processing core and a second set of at least one of the plurality of non-volatile logic element arrays is associated with a second function of the computing device apparatus associated with the processing core; wherein operation of the first set of at least one of the plurality of non-volatile logic element arrays is independent of operation of the second set of at least one of the plurality of non-volatile logic element arrays;
a second power domain configured to supply power to logic elements configured to control signals for storing data to or reading data from the plurality of non-volatile logic element arrays; a third power domain configured to supply power for the plurality of non-volatile logic element arrays; wherein individual ones of the first power domain, the second power domain, and the third power domain are configured to be powered down or up independently of other ones of the first power domain, the second power domain, and the third power domain;
wherein the third power domain is configured to be powered down during regular operation of the computing device apparatus.