Predicate counter

摘要

According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

主权项

1. A processor, comprising:
a processing element; a sequencer configured to provide a conditionally-executable instructions to the processing element, wherein a condition is provided by a predicate encoded in a predicate counter; and a predicate counter register configured to receive more than two meaningful values and to provide its value as the predicate counter; wherein the processor includes circuitry to provide IF, ELSE, and ENDIF primitives that are dependent on the predicate counter; wherein the IF primitive comprises: receiving a condition; if the predicate counter is not zero, incrementing the predicate counter; if the predicate counter is zero and the condition is false, setting the predicate counter to one; wherein the ELSE primitive comprises: if the predicate counter is zero, setting the predicate counter to one; and if the predicate counter is one, setting the predicate counter to zero; wherein the ENDIF primitive comprises: if the predicate counter is not zero, decrementing the predicate counter.