| 主权项 |
1. A GOA circuit structure, comprising multiple twined GOA units cascaded with each other, assuming N is natural number, the N-level GOA unit charging the N-level horizontal scanning line in the displaying area, each said twined GOA unit comprising the (2N−1)-level GOA unit and the 2N-level GOA unit, the (2N−1)-level GOA unit comprising a first pull-down holding circuit and a second pull-down holding circuit respectively connected with the (2N−1)-level gate signal point and the (2N−1)-level horizontal scanning line, the 2N-level GOA unit comprising a third pull-down holding circuit and a fourth pull-down holding circuit respectively connected with the 2N-level gate signal point and the 2N-level horizontal scanning line; the (2N−1)-level gate signal point being further connected with the third pull-down holding circuit and the fourth pull-down holding circuit respectively, the 2N-level gate signal point being further connected with the first pull-down holding circuit and the second pull-down holding circuit respectively;
the first pull-down holding circuit comprising: a first thin film transistor, the gate thereof inputting a second clock signal, the source and the drain thereof respectively inputting a first clock signal and being connected to a first circuit point, the first pull-down holding circuit working or not depending on the potential level of the first circuit point; the second pull-down holding circuit comprising: a second thin film transistor, the gate thereof inputting a fourth clock signal, the source and the drain thereof respectively inputting a third clock signal and being connected to a second circuit point, the second pull-down holding circuit working or not depending on the potential level of the second circuit point; the third pull-down holding circuit comprising: a third thin film transistor, the gate thereof inputting a third clock signal, the source and the drain thereof respectively inputting a second clock signal and being connected to a third circuit point, the third pull-down holding circuit working or not depending on the potential level of the third circuit point; the fourth pull-down holding circuit comprising: a fourth thin film transistor, the gate thereof inputting a first clock signal, the source and the drain thereof respectively inputting a fourth clock signal and being connected to a fourth circuit point, the fourth pull-down holding circuit working or not depending on the potential level of the fourth circuit point; the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal being provided to make the first pull-down holding circuit, the second pull-down holding circuit, the third pull-down holding circuit, and the fourth pull-down holding circuit work alternately; wherein a first pull-up clock signal, a second pull-up clock signal, a third pull-up clock signal, and a fourth pull-up clock signal are respectively input into the pull-up circuits of the (2N−1)-level, the 2N-level, the (2N+1)-level, and the (2N+2)-level GOA units to respectively charge the corresponding horizontal scanning line in the displaying area, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal respective correspond to the first pull-up clock signal, the second pull-up clock signal, the third pull-up clock signal, and the fourth pull-up clock signal; wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal respectively correspond to four low-frequency clock signals; wherein the first pull-down holding circuit further comprises: a fifth thin film transistor, the gate thereof being connected to the (2N−1)-level gate signal point, the source and the drain thereof being respectively connected to the first circuit point and inputting a DC low voltage, a sixth thin film transistor, the gate thereof being connected to the first circuit point, the source and the drain thereof being respectively connected to the (2N−1)-level gate signal point and inputting the DC low voltage, a seventh thin film transistor, the gate thereof being connected to the first circuit point, the source and the drain thereof being respectively connected to the (2N−1)-level horizontal scanning line and inputting the DC low voltage, and an eighth thin film transistor, the gate thereof being connected to the 2N-level gate signal point, the source and the drain thereof being respectively connected to the first circuit point and inputting the DC low voltage; wherein the second pull-down holding circuit further comprises: a ninth thin film transistor, the gate thereof being connected to the (2N−1)-level gate signal point, the source and the drain thereof being respectively connected to the second circuit point and inputting the DC low voltage, a tenth thin film transistor, the gate thereof being connected to the second circuit point, the source and the drain thereof being respectively connected to the (2N−1)-level gate signal point and inputting the DC low voltage, an eleventh thin film transistor, the gate thereof being connected to the second circuit point, the source and the drain thereof being respectively connected to the (2N−1)-level horizontal scanning line and inputting the DC low voltage, and a twelfth thin film transistor, the gate thereof being connected to the 2N-level gate signal point, the source and the drain thereof being respectively connected to the second circuit point and inputting the DC low voltage; wherein the third pull-down holding circuit further comprises: a thirteenth thin film transistor, the gate thereof being connected to the (2N−1)-level gate signal point, the source and the drain thereof being respectively connected to the third circuit point and inputting the DC low voltage, a fourteenth thin film transistor, the gate thereof being connected to the third circuit point, the source and the drain thereof being respectively connected to the 2N-level gate signal point and inputting the DC low voltage, a fifteenth thin film transistor, the gate thereof being connected to the third circuit point, the source and the drain thereof being respectively connected to the 2N-level horizontal scanning line and inputting the DC low voltage, and a sixteenth thin film transistor, the gate thereof being connected to the 2N-level gate signal point, the source and the drain thereof being respectively connected to the third circuit point and inputting the DC low voltage; wherein the fourth pull-down holding circuit further comprises: a seventeenth thin film transistor, the gate thereof being connected to the (2N−1)-level gate signal point, the source and the drain thereof being respectively connected to the fourth circuit point and inputting the DC low voltage, an eighteenth thin film transistor, the gate thereof being connected to the fourth circuit point, the source and the drain thereof being respectively connected to the 2N-level gate signal point and inputting the DC low voltage, a nineteenth thin film transistor, the gate thereof being connected to the fourth circuit point, the source and the drain thereof being respectively connected to the 2N-level horizontal scanning line and inputting the DC low voltage, and a twentieth thin film transistor, the gate thereof being connected to the 2N-level gate signal point, the source and the drain thereof being respectively connected to the fourth circuit point and inputting the DC low voltage. |
