Magnetic memory device and method of forming thereof

摘要

A device and a method of forming a device are presented. A substrate is provided. Front end of line processing is performed to form circuit component on the substrate and back end of line processing is performed to include the uppermost inter level dielectric (ILD) layer. The uppermost ILD layer includes first and second interconnects. A pad level is formed over the uppermost ILD layer. A storage unit of a memory cell is provided in the pad level. The storage unit is coupled to the first interconnect of the uppermost ILD layer. A cell interconnect and a pad interconnect are formed in the pad level. The cell interconnect is formed on top of and coupled to the storage unit and the pad interconnect is coupled to the second interconnect in the uppermost ILD layer.

主权项

1. A method of forming a device comprising:
providing a substrate; performing front end of line processing to form circuit components on the substrate; and performing back end of line processing to form an uppermost inter level dielectric (ILD) layer of the device, the uppermost ILD layer includes a metal level over a via level, wherein the metal level comprises first and second metal lines having top surfaces which are coplanar with a top surface of the uppermost ILD layer; forming a pad level over the uppermost ILD layer, wherein forming the pad level comprises
forming a lower passivation layer and an intermediate dielectric layer over the lower passivation layer, andpatterning the lower passivation and intermediate dielectric layers to form a pad via opening which exposes a portion of the top surface of the second metal line in the uppermost ILD layer; providing a storage unit of a memory cell in the pad level, wherein a bottom surface of the storage unit completely contacts the top surface of the first metal line of the uppermost ILD layer without covering the entire first metal line, and wherein top surface of the storage unit is coplanar with top surface of the intermediate dielectric layer; and forming a cell interconnect and a pad interconnect in the pad level, wherein forming the cell interconnect and the pad interconnect comprises
forming a conductive layer over the intermediate dielectric layer, wherein the conductive layer fills the pad via opening, andpatterning the conductive layer to simultaneously form the cell interconnect and pad interconnect, wherein the cell interconnect is a cell contact pad which is formed on top of and in direct contact with the top surfaces of the storage unit and the intermediate dielectric layer while the pad interconnect includes a pad via contact and a contact pad, wherein the pad via contact extends beyond a bottom surface of the intermediate dielectric layer to be in direct contact with the exposed portion of the second metal line and the contact pad is disposed on the intermediate dielectric layer.