Vertical compound semiconductor field effect transistor on a group IV semiconductor substrate

摘要

Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor material. A cavity is formed to physically expose a top surface of the handle substrate through a stack, from bottom to top, of a buried insulator layer, a doped semiconductor material portion in a top semiconductor layer, and a dielectric material layer. A gate dielectric is formed around the cavity by a conformal deposition of a dielectric material layer and an anisotropic etch. A lower active region, a channel region, and an upper active region are formed by selective epitaxy processes in, and/or above, the trench and from the top surface of the handle substrate. The selective epitaxy processes deposit a compound semiconductor material. The doped semiconductor material portion functions as the gate of a vertical compound semiconductor field effect transistor.

主权项

1. A semiconductor structure comprising:
a handle substrate including a doped Group IV semiconductor well; an insulator layer overlying said handle substrate; a doped semiconductor material portion overlying a first portion of said insulator layer that is located over said doped Group IV semiconductor well; a vertical stack including a lower active region and a channel region, said vertical stack extending at least through said first portion of said insulator layer and said doped semiconductor material portion and laterally surrounded by a gate dielectric contacting sidewalls of said first portion of said insulator layer and said doped semiconductor material portion, and wherein said lower active region and said channel region comprise at least one compound semiconductor material; and a field effect transistor overlying a second portion of said insulator layer, said field effect transistor comprising active regions composed of a same Group IV semiconductor material as said doped semiconductor material portion, wherein top surfaces of said active regions of said field effect transistor are coplanar with a top surface of said doped semiconductor material portion.