发明名称 Semiconductor storage device
摘要 A semiconductor storage device has a cell array, a redundant array provided logically separated from the cell array, a cache memory having a storing area of data read from or written in the cell array by one access, defective column storage to store a column address of a defective column in the cell array, a defective column determination module to determine whether a column address to be accessed matches the column address stored in the defective column storage, and a clock generator to generate a clock for accessing each of the divided areas for each period of the interleave access and, when the defective column determination module determines that there is a match, instead of a clock accessing a divided page buffer area at the generation timing of the clock accessing the divided page buffer area.
申请公布号 US9343186(B2) 申请公布日期 2016.05.17
申请号 US201414482697 申请日期 2014.09.10
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Komai Hiromitsu
分类号 G06F12/00;G06F13/00;G11C29/00;G06F12/06 主分类号 G06F12/00
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P
主权项 1. A semiconductor storage device comprising: a cell array; a redundant array provided logically separated from the cell array, the redundant array comprising a column area replaceable with a defective column in the cell array; a cache memory comprising a storing area of data read from or written in the cell array by one access, the cache memory allowing interleave access to a plurality of divided areas to which the area is logically divided; a defective column storage to store a column address of a defective column in the cell array; a defective column determination module to determine whether a column address to be accessed matches the column address stored in the defective column storage; and a clock generator to generate a clock for accessing each of the divided areas for each period of the interleave access and, when the defective column determination module determines that there is a match, instead of a clock accessing a divided page buffer area that corresponds to the defective column, at the generation timing of the clock accessing the divided page buffer area, to generate a clock accessing the redundant array that has stored data of the defective column.
地址 Minato-ku JP
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