发明名称 |
POWER OVERLAY STRUCTURE HAVING WIREBONDS AND METHOD OF MANUFACTURING THE SAME |
摘要 |
PROBLEM TO BE SOLVED: To provide a method for fabricating an I/O interconnection.SOLUTION: A power overlay (POL) structure includes: a power device having at least one upper contact pad disposed on an upper surface of the power device; and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer, and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.SELECTED DRAWING: Figure 1 |
申请公布号 |
JP2016082230(A) |
申请公布日期 |
2016.05.16 |
申请号 |
JP20150198983 |
申请日期 |
2015.10.07 |
申请人 |
GENERAL ELECTRIC CO <GE> |
发明人 |
GOWDA ARUN VIRUPAKSHA;MCCONNELEE PAUL ALAN |
分类号 |
H01L21/60;H01L25/07;H01L25/18 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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