| 摘要 |
PROBLEM TO BE SOLVED: To provide a delay circuit capable of coping with wide bandwidth clocks, a phase locked loop having the delay circuit, and a processor having the phase locked loop.SOLUTION: A delay circuit includes: a plurality of delay buffers having two or more delay units connected in series, and capable of variably controlling its delay amount, respectively; a variable control voltage generation circuit for supplying a variable control voltage for controlling a delay amount of first delay units, to the first delay units that the plurality of delay buffers have, respectively; and a fixed control voltage generation circuit for supplying a fixed control voltage of any of a plurality of fixed control voltages for controlling a delay amount of a second delay unit, to second delay units that the plurality of delay buffers have, respectively. The plurality of delay buffers are connected in series and an input signal propagates in the plurality of delay buffers connected in series.SELECTED DRAWING: Figure 8 |
