| 摘要 |
The embodiment of the present invention relates to a memory system and a system on chip (SoC) connected with a plurality of memory chips. The SoC includes first and second processors, a first access window, a first linear re-mapper, and a memory controller. The first and second processors are configured to provide an address for using the memory chips. The first access window sets an area, which is accessed only by the first processor, from among one or more address areas of the memory chips. The first linear re-mapper remaps the address received from the first processor and creates the re-mapped address. The memory controller performs a partial linear access operation with respect to the memory chips, based on an area set by the first access window and an address remapped by the first linear re-mapper. According to the present invention, the access window and the linear re-mapper are connected between the processors and the memory controller, so that power consumption can be reduced, and the memory can be efficiently used. |
