| 发明名称 |
ADDER DECODER |
| 摘要 |
The present disclosure relates to an add and decode hardware logic circuit for adding two n bit inputs, A and B. A series of n logic stages are each configured to perform a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m<n, perform a second operation of performing a bitwise left shift by 2m of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 1, or perform a third operation of performing a bitwise left shift by 2m+1 of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 2. An output at the last stage provides a decoded sum of the inputs A and B. |
| 申请公布号 |
US2016132294(A1) |
申请公布日期 |
2016.05.12 |
| 申请号 |
US201414538484 |
申请日期 |
2014.11.11 |
| 申请人 |
Cavium, Inc. |
发明人 |
Beckman Edward;Mohan Nitin |
| 分类号 |
G06F7/50;G06F5/01 |
主分类号 |
G06F7/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An add and decode hardware logic circuit, comprising:
n bit inputs, A and B, wherein n is greater than 1; n logic stages, each logic stage configured to:
perform a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m<n;perform a second operation of performing a bitwise left shift by 2m of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 1;perform a third operation of performing a bitwise left shift by 2m+1 of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 2; an output at stage n providing a decoded sum of inputs A and B. |
| 地址 |
San Jose CA US |
