| 摘要 |
In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer. |
| 主权项 |
1. A circuit comprising:
a first differential input buffer configured to receive a differential strobe signal from a pseudo open drain output buffer, the differential strobe signal including a first component and a second component, the differential strobe signal including at least three time periods including:
a deterministic tri-state period during which both the first component and the second component are simultaneously at a first logic state;a preamble period after the tri-state period including:
a first transition period during which the second component transitions from the first logic state to a second logic state,a first holding period after the first transition period during which the first component is at the first logic state and the second component is at the second logic state,a second transition period after the first holding period during which the first component transitions to the second logic state and during which the second component transitions to the first logic state, anda second holding period after the second transition period during which the first component is at the second logic state and the second component is at the first logic state; anda burst period after the preamble period including a burst of alternating first and second clock edges; a second input buffer configured to receive the first component of the differential strobe signal; a control logic block configured to receive an output of the second input buffer, detect the transition of the first component from the first logic state to the second logic state during the preamble period, and assert an enable signal in response to the detection of the transition; and a gating logic block configured to receive the asserted enable signal and the differential strobe signal, and to un-gate an output of the first differential input buffer during the second holding period in response to receiving the asserted enable signal. |
