SLEEP MODE OPERATION FOR VOLATILE MEMORY CIRCUITS

摘要

Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data.

主权项

1. An apparatus, comprising:
a volatile memory circuit; and a control circuit configured and arranged to
generate and store parity data for data blocks written to the volatile memory circuit;in response to a first control signal, place the volatile memory circuit in a sleep mode, in which a supply voltage for the volatile memory is set to a first voltage at which data blocks stored in the volatile memory circuit are subject to an introduction of errors; andin response to a second control signal,
place the volatile memory into an active mode, anddetect and correct errors in the data blocks stored in the volatile memory using the stored parity data.