INDEPENDENT ASYNCHRONOUS FRAMEWORK FOR EMBEDDED SUBSYSTEMS

摘要

An integrated circuit is provided with an independent power framework for a first subsystem and another independent power framework for a processor subsystem that receives messages from the first subsystem.

主权项

1. An integrated circuit, comprising a first subsystem including core logic coupled to a first subsystem core logic power rail and embedded memories coupled to a first subsystem memory power rail, wherein the first subsystem core logic includes a first subsystem power manager unit (PMU);
a processor subsystem including core logic coupled to a processor core logic power rail and embedded memories coupled to a processor memory power rail; and an always-on (AON) power domain including a first subsystem always-on power manager (AON-PM), wherein the first subsystem AON-PM is configured to control a voltage for the first subsystem core logic power rail and a voltage for the first subsystem memory power rail depending upon the whether the first subsystem is to operate in a sleep mode or in a nominal mode of operation, and wherein the first subsystem PMU is configured to transmit a wakeup period to the AON-PM prior to a transition to the sleep mode and wherein the first subsystem AON-PM is further configured to time the wakeup period responsive to a sleep clock and signal the end of the wakeup period to the first subsystem PMU to begin a transition of the first subsystem from the sleep mode to the nominal mode of operation.