| 摘要 |
A memory access unit (24; 741,...,74m) for handling transfers of samples in a d- dimensional array between a one of m data buses (27; 77), where m ≥ 1, and k*m memories (221,...,22k; 721,...,72k*m), where k ≥ 2, is disclosed. The memory access unit comprises k address calculators (281,...,28k; 791,...,79k), each address calculator configured to receive a bus address (A_B) to add a respective offset to generate a sample bus address (Α_Β') and to generate, from the sample bus address according to an addressing scheme, a respective address (A_1,..., A_d) in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors (291,...,29k; 801,...,80k*m), each sample collector operable to generate a memory select (CS) for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories. Each sample collector (291,...,29k; 801,...,80k*m) is configured to calculate a respective memory select in dependence upon the address in each of the d dimensions such that each sample collector selects a different one of the k*m memories so as to allow the sample collectors to access k of the k*m memories concurrently. A memory controller may comprise m memory access units (741,...,74m) for handling transfers of samples in a d-dimensional array between m data buses (771,...,77m) and K*m memories (711,...,71k*m). |
