SIGNAL INTEGRITY IN MUTLI-JUNCTION TOPOLOGIES

摘要

A channel (e.g., memory channel) coupling a processor to multiple devices (e.g., DIMMs) is described. The channel has an interconnect topology with multiple interconnect portions coupled together with two or more junctions. At least one of these junctions has first and second interconnect portions that cross each other to form a plus-shaped junction. Also, the interconnect routing between the two or more junctions has an impedance matched to impedance of the two or more junctions.

主权项

1. A system comprising:
a processor; a plurality of devices; and a channel coupling the processor to the plurality of devices, the channel having an interconnect topology with a plurality of interconnect portions coupled together with two or more junctions, at least one of the two or more junctions having first and second interconnect portions that cross each other to form a plus-shaped junction, and wherein interconnect routing between the two or more junctions having an impedance matched to impedance of the two or more junctions.