发明名称 |
DYNAMIC MARGIN TUNING FOR CONTROLLING CUSTOM CIRCUITS AND MEMORIES |
摘要 |
Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may be configured to monitor a voltage level of a power supply coupled to the custom circuit or memory. A delay amount of a delay unit within the custom circuit or memory may be changed in response to a determination that the voltage level of the power supply has changed. |
申请公布号 |
WO2016022291(A4) |
申请公布日期 |
2016.05.12 |
申请号 |
WO2015US41496 |
申请日期 |
2015.07.22 |
申请人 |
APPLE INC. |
发明人 |
BHATIA, AJAY KUMAR |
分类号 |
H03K5/13;G01R19/00;G01R31/40;G06F1/24;G06F1/30;G11C7/12;G11C7/22;H03K5/00;H03K19/003 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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