| 摘要 |
PROBLEM TO BE SOLVED: To allow an arrangement of a plurality of lower diffusion layer power feeding contact plugs in parallel with a plurality of semiconductor pillars while inhibiting an increase in parasitic capacitance occurring between the lower diffusion layer power feeding contact plugs and a gate electrode.SOLUTION: A semiconductor device 1 comprises: circular pillars SP1-SP3 which are semiconductor pillars vertically arranged on a semiconductor substrate 2 and arranged in parallel with each other along a y direction; beam pillars BP1, BP2 which are semiconductor pillars vertically arranged on the semiconductor substrate 2 and connected to the neighboring two circular pillars, respectively; a lower diffusion layer 7 formed in contact with a bottom edge of a composite pillar P composed of the circular pillars SP1-SP3 and the beam pillars BP1, BP2; a gate electrode 11 which covers a lateral face of the composite pillar P via a gate insulation film 10; and lower diffusion layer power feeding contact plugs LP1, LP2 which are connected to the lower diffusion layer 7 by under surfaces of the lower diffusion layer power feeding contact plugs LP1, LP2 and arranged at positions in an x direction, which face lateral faces of the beam pillars BP1, BP2, respectively.SELECTED DRAWING: Figure 1 |
