发明名称 METHOD OF FABRICATING INTEGRATED CIRCUIT
摘要 A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern and a first alignment mark and a second reticle is used to form a second pattern and a second alignment mark in a same layer. A third reticle is aligned to the first alignment mark and the second alignment mark, to obtain an overlay correction value; additionally, a third reticle is aligned to the first alignment mark to obtain a first overlay correction value, a third reticle is aligned to the second alignment mark to obtain a second overlay correction value, and a total overlay correction value is obtained by trading off the first overlay correction value and the second overlay correction value. The third reticle is used to form a third pattern by aligning the third reticle with the total overlay correction value.
申请公布号 US2016133510(A1) 申请公布日期 2016.05.12
申请号 US201414534180 申请日期 2014.11.06
申请人 UNITED MICROELECTRONICS CORP. 发明人 Tung Yu-Cheng
分类号 H01L21/768 主分类号 H01L21/768
代理机构 代理人
主权项 1. A method of fabricating an integrated circuit, comprising: using a first reticle to form a first pattern and a first alignment mark and using a second reticle to form a second pattern and a second alignment mark; aligning a third reticle to the first alignment mark and the second alignment mark, to obtain an overlay correction value; and using the third reticle to form a third pattern through a lithography apparatus by aligning the third reticle with the overlay correction value.
地址 Hsin-Chu City TW