| 摘要 |
Disclosed are a method for minimizing a chip test time and an apparatus thereof. The apparatus divides scan patterns into at least two scan sections, and determines a second shift frequency smaller than a first shift frequency as the shift frequency of each scan section after checking the first shift frequency when the output pattern of the scan chain is different from a prediction pattern by an increase/decrease in a shift frequency, with regard to each scan section. Also, a burn-in test time can be minimized and the quality of the burn-in test can be improved. |
