Method, apparatus, and system for speculative abort control mechanisms

摘要

An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

主权项

1. A system comprising:
a plurality of cores, one or more of the plurality of cores to concurrently execute multiple threads; one or more of the plurality of cores to perform out-of-order execution of instructions of the threads; one or more of the plurality of cores comprising:
instruction fetch logic to fetch instructions of one or more of the threads,instruction decode logic to decode the instructions,register renaming logic to rename one or more registers within a register file,a data cache to cache data,a translation lookaside buffer to store virtual to physical address translations,a second level cache unit to cache instructions and data, andan execution unit to execute a first instruction to indicate an end of the transaction execution region and to cause memory transactions to be atomically committed or aborted; and one or more integrated memory controllers to communicatively couple the plurality of cores to dynamic random access system memory.