| 发明名称 |
SYSTEM AND METHOD FOR CONTROLLING IDLE STATE EXITS TO MANAGE DI/DT ISSUES |
| 摘要 |
A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time. |
| 申请公布号 |
US2016132096(A1) |
申请公布日期 |
2016.05.12 |
| 申请号 |
US201514937290 |
申请日期 |
2015.11.10 |
| 申请人 |
International Business Machines Corporation |
发明人 |
ALLEN-WARE Malcolm S.;DRAKE Alan James;FLOYD Michael Stephen;LEFURGY Charles Robert;RAJAMANI Karthick;WEBEL Tobias |
| 分类号 |
G06F1/32 |
主分类号 |
G06F1/32 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises:
detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when a number of idle state exits exceeds a predetermined threshold idle state exit number. |
| 地址 |
Amonk NY US |
