| 主权项 |
1. An N-bit Gray counter, with N an integer greater than 1, comprising a string of N logic cells connected in cascade, wherein each said logic cell comprises an input port for a succession of clock pulses and a generating circuit for generating a Gray count bit having an output port for the said Gray count bit, wherein each said logic cell, except at most the last logic cell, of the string also comprises a circuit for generating a clock signal having a clock output port linked to the input port of the following logic cell, and wherein:
each said circuit for generating a clock signal is adapted for authorizing the passage to the clock output port of one clock pulse out of two present at the input port and for prohibiting the passage of the following clock pulse; the generating circuit for generating a Gray count bit for each said logic cell, with the exception of the last logic cell of the string, is adapted for inverting the value of the count bit present at its output port each time that the circuit for generating a clock signal of the corresponding logic cell prohibits the passage of a said clock pulse, and for maintaining the value unchanged in the converse case; and the generating circuit for generating a Gray count bit for the last logic cell of the string is adapted for inverting the value of the count bit present at its output port each time that a clock pulse is present at the input port of the last logic cell. |
