MULTIPLE-CAPTURE DFT METHOD FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SELF-TEST OR SCAN-TEST

摘要

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

主权项

1. A computer-aided design (CAD) method for generating a testable hardware description language (HDL) code or netlist to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test mode or scan-test mode, where N>1, the integrated circuit or circuit assembly being represented by an HDL code or netlist, each clock domain having one or more clocks and one or more scan cells, said CAD method comprising using a computer for: (a) performing self-test synthesis or scan synthesis on said HDL code or netlist for generating said testable HDL code or netlist in accordance with a multiple-capture design-for-test (DFT) technique; and (b) generating HDL test benches for verifying the correctness of said testable HDL code or netlist in said self-test mode or said scan-test mode.