发明名称 METHOD OF PATTERNING INCORPORATING OVERLAY ERROR PROTECTION
摘要 Techniques herein include use of a spacer processes for patterning flows during microfabrication for creating hardmasks, features, contact openings, etc. Techniques herein include using a sidewall spacer to define a hard border between features to be patterned. Such a spacer is positioned underneath an overlying relief pattern so that a portion of the spacer is exposed and protecting an underlying layer. Techniques herein can be used for metallization, and, in particular, metallization of a first metal layer above electronic device contacts. More broadly, techniques herein can be used for any type of critical placement where one structure is extremely close to another structure, such as with sub-resolution dimensions.
申请公布号 WO2016073077(A1) 申请公布日期 2016.05.12
申请号 WO2015US52233 申请日期 2015.09.25
申请人 TOKYO ELECTRON LIMITED;TOKYO ELECTRON U.S. HOLDINGS, INC. 发明人 DEVILLIERS, ANTON J.;SMITH, JEFFREY
分类号 H01L21/027 主分类号 H01L21/027
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