发明名称 PLL SPEED CONTROL CIRCUIT
摘要 PURPOSE:To enable the synchronous operation at a specified speed ratio of first and second controlled systems by respectively reducing phase differences between first and second reference pulses and encoder pulses to zero in the stage of a negative feedback. CONSTITUTION:Phase differences between reference pulses TREFa, TREFb and encoder pulses XFBa, XFBb are outputted as the numbers of clock pulses T and their data P1ER, P2ER are subjected to a specified operation in phase difference correctors 8a, 8b. Data PERa, PERb for giving the magnitude of absolute phase differences between said reference pulses TREFa, TREFb and encoder pulses XFBa, XFBb are given as feedback quantities to regulators 9a, 9b for regulating the controlled variable of controlled systems 10a, 10b so that the magnitude of said absolute phase differences between said reference pulses TREFa, TREFb and encoder pulses XFBa, XFBb is reduced to zero. Thus, said controlled systems 10a, 10b can be operated synchronously at a specified speed ratio.
申请公布号 JPH02307385(A) 申请公布日期 1990.12.20
申请号 JP19890129371 申请日期 1989.05.22
申请人 SHARP CORP 发明人 ISHII HIROSHI;OZAKI MASAAKI
分类号 G03G15/04;G03B27/50;G05D13/62;H02P5/52;H02P25/06 主分类号 G03G15/04
代理机构 代理人
主权项
地址