发明名称 |
SEMICONDUCTOR CIRCUIT, VOLTAGE DETECTION CIRCUIT, AND VOLTAGE DETERMINATION CIRCUIT |
摘要 |
The present disclosure provides a semiconductor circuit including: a PMOS transistor that includes a first source connected to a power supply, a first drain, and a first gate to which a fixed potential is supplied; an output circuit that outputs a first output signal, which is a reset signal or a power-on signal, and that outputs a second output signal according to a potential of the first drain; a constant current source connected to the first drain; and an NMOS transistor that includes a second source to which a fixed potential is supplied, a second drain connected to the first drain, and a second gate to which the second output signal from the output circuit is applied. |
申请公布号 |
US2016134274(A1) |
申请公布日期 |
2016.05.12 |
申请号 |
US201514936167 |
申请日期 |
2015.11.09 |
申请人 |
LAPIS SEMICONDUCTOR CO., LTD. |
发明人 |
TAKEMURA Takashi |
分类号 |
H03K17/22 |
主分类号 |
H03K17/22 |
代理机构 |
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代理人 |
|
主权项 |
1. A semiconductor circuit comprising:
a PMOS transistor that includes a first source connected to a power supply, a first drain, and a first gate to which a fixed potential is supplied; an output circuit that outputs a first output signal, which is a reset signal or a power-on signal, and that outputs a second output signal according to a potential of the first drain; a constant current source connected to the first drain; and an NMOS transistor that includes a second source to which a fixed potential is supplied, a second drain connected to the first drain, and a second gate to which the second output signal from the output circuit is applied. |
地址 |
Kanagawa JP |