发明名称 |
SYSTEM AND METHOD FOR AN ASYNCHRONOUS PROCESSOR WITH PIPELINED ARITHMETIC AND LOGIC UNIT |
摘要 |
Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction. |
申请公布号 |
EP3017363(A1) |
申请公布日期 |
2016.05.11 |
申请号 |
EP20140843033 |
申请日期 |
2014.09.09 |
申请人 |
HUAWEI TECHNOLOGIES CO., LTD. |
发明人 |
SHI, WUXIAN;GE, YIQUN;ZHANG, QIFAN;HUANG, TAO;TONG, WEN |
分类号 |
G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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