THE METHOD AND APPARATUS FOR CONTROLLING LOGIC OF FAST CURRENT MODE

摘要

Disclosed are an apparatus and a method for controlling logic in a fast current mode, which can prevent an operation delay by a parasitic capacitor without any capacitors requiring an excessive chip space. The method for controlling logic in a fast current mode includes the steps of: allowing a reference current to flow into a first transistor of a multi-level active bias device and a third transistor for determining a bias voltage when a first switch of the multi-level active bias device is turned on and a second switch is turned off in a sleep mode; allowing the reference current to flow into the third transistor when the first and second switches are turned off in a fast wake-up mode; allowing the reference current to flow into the second and third transistors when the first switch is turned off and the second switch is turned on in a general operation mode; and allowing the reference current to flow into the first to third transistors when the first and second switches are turned on in a fast turning-off mode.