| 发明名称 | Memory and memory system including the same | ||
| 摘要 | A memory includes a plurality of word lines, a measurement block suitable for measuring an active duration of an activated word line among the multiple word lines, and a refresh circuit suitable for controlling a refresh operation to refresh one or more of the multiple word lines adjacent to the activated word line when the active duration exceeds a predetermined threshold. | ||
| 申请公布号 | US9336852(B2) | 申请公布日期 | 2016.05.10 |
| 申请号 | US201414333300 | 申请日期 | 2014.07.16 |
| 申请人 | SK Hynix Inc. | 发明人 | Lim Yu-Ri;Cho Jin-Hee;Park Jung-Hoon |
| 分类号 | G11C7/00;G11C11/406 | 主分类号 | G11C7/00 |
| 代理机构 | IP & T Group LLP | 代理人 | IP & T Group LLP |
| 主权项 | 1. A memory, comprising: a plurality of word lines; a measurement block suitable for measuring an active duration of an activated word line among the multiple word lines; and a refresh circuit suitable for controlling a refresh operation to refresh one or more of the multiple word lines adjacent to the activated word line when the active duration is measured to exceed a threshold. | ||
| 地址 | Gyeonggi-do KR | ||